1. Technical Field
The present invention relates generally to picture display apparatus and more particularly, to a picture display apparatus such as a CRT display, a so-called video movie camera (or a video camera) and an analog character display apparatus having the function of superimposing fringed characters or patterns on an image.
2. Background Art
FIG. 6 is a block diagram illustrating a display apparatus having character display functions, such as a video movie camera and an analog character display apparatus heretofore in use for displaying analog images and characters (hereinafter simply called "character display equipment"), mainly depicting the character image signal generating circuitry.
The character image signal generating circuit 13 is provided with a display data RAM 5 for storing all character codes to be displayed on a picture at a time.
In order to write a character code "W" supplied from a microcomputer 1 to the display data RAM 5, this circuit is provided with a write address register 2, a write data register 3, a write synchronizing circuit 4, and an address selecting circuit 6. The write address register 2 receives a control/data signal B from the microcomputer 1 and holds an address signal A therein. The write data register 3 holds the character code "W" and applies it as a character signal W. The write synchronizing circuit 4 generates a write synchronizing signal S according to the control signal of the control/data signal B. Further, the address selecting circuit 6 generates an address signal U directed to the display data RAM 5 on receiving the write signal S.
In order to read a display character code "G" from the display data RAM 5, the character image signal generating circuit 13 is provided with a vertical address counter 12, an oscillating circuit 11 and a horizontal address counter 10. The vertical address counter 12 generates a line selecting signal R for determining a vertical position on a display picture on receiving a vertical synchronizing signal V and a horizontal synchronizing signal H in synchronization with a scanning line, and applies the line selecting signal R to the address selecting circuit 6. The oscillating circuit 11 generates a so-called dot clock D on receiving the horizontal synchronizing signal H synchronous with the oscillation starting phase thereof and having a period corresponding to the horizontal scanning interval of each display dot on the display picture so as to obtain timing during the horizontal scanning. The horizontal address counter 10 generates a column selecting signal C on receiving the horizontal synchronizing signal H and the dot clock D for determining a horizontal position on the display picture and applies the column selecting signal C to the address selecting circuit 6 and the write synchronizing circuit 4.
In order to display a pattern of the character code "G" thus selected, the character image signal generating circuit 13 is further provided with a character generator 7 and a parallel/serial converter circuit 8 (hereinafter called a serial converter circuit 8). The character generator 7 generates a character pattern "P" equivalent to one line out of the pattern equivalent to one character on receiving an address signal L generated in the address selecting circuit 6 and the character code "G" on the character signal G. The serial converter circuit 8 sequentially outputs a character pattern having a plurality of bits equivalent to one line dot-by-dot through the dot clock D. That output is combined with another image signal E before being applied to CRT 9 on which a superimposed image is displayed.
The serial converter circuit 8 has a circuit for generating fringed patterns and also can combine the character pattern "P" having a fringed pattern "Y" with the image signal E to make CRT 9 display the combination.
Although the address selecting circuit 6 has been so defined since it selects either the address supplied from the outside or what is internally produced and gains access to the display data RAM 5, it functions as an access circuit with respect to the display data RAM 5 and the character generator 7.
A description will subsequently be given of the operation of the character image signal generating circuit 13 thus arranged when the character code "W" supplied from the microcomputer 1 is written to the display data RAM 5.
When the microcomputer 1 supplies a character code "W" to be written to the display data RAM 5 as its data to the write data register 3 according to the control/data signal B, the write data register 3 as a recipient holds the data as the character code "W" and then supplies the data onto the character signal W. When the microcomputer 1 supplies an address "A" in the display data RAM 5 to be written thereto as its data to the address register 2 according to the control/data signal B, the write address register 2 as a recipient holds the address "A" and supplies it onto the address signal A. When the microcomputer 1 communicates to the write synchronizing circuit 4 that the write address register 2 and the write data register 3 respectively hold the address signal A and the character code "W" in the form of a control signal according to the control/data signal B and ready for the write operation, the write synchronizing circuit 4 as a recipient tries to send out a write synchronizing signal S for effecting the write operation.
At this time, however, the write synchronizing circuit 4 outputs the write synchronizing signal S while avoiding the timing at which the character code "G" during a period of scanning an ineffective picture necessitating no character signal G is being read from the display data RAM 5, since the display character code "G" selected by the address signal U generated by the address selecting circuit 6 that has received the line selecting signal R and the column selecting signal C is read in synchronization with the horizontal synchronizing signal H and the vertical synchronizing signal V. The illustration of an input signal directed to the write synchronizing circuit 4 necessary for making the above-noted decision has been omitted in FIG. 3. On receiving the write synchronizing signal S, the address selecting circuit 6 selects the address signal A and supplies the address "A" on the address signal A to the display data RAM 5 as the address signal U together with the write signal, whereby the character code "W" is written to the address "A" in the display data RAM 5 on receiving the address signal U and the character signal W.
A description will subsequently be given of the operation of the circuit at the time the character code "G" to be displayed is selected and read from the display data RAM 5.
On receiving the vertical synchronizing signal V, the vertical address counter 12 initializes its count and on receiving the horizontal synchronizing signal H, counts up the value and outputs the line selecting signal R for determining the vertical position of a scanning line. On receiving the horizontal synchronizing signal H, the oscillation circuit 11 initializes the oscillation phase, and generates and outputs the dot clock D of a frequency corresponding to the horizontal scanning speed of the scanning line. On receiving the horizontal synchronizing signal H, the horizontal address counter 10 initializes its count and on receiving the dot clock D, counts up the value and outputs the column selecting signal C for determining the horizontal position of the scanning line. The address selecting circuit 6 receives the line address signal R and the column address signal C thus generated, generates the address signal U intended for the display data RAM 5 and the address signal L intended for the character generator 7 by subjecting these address signals to computation in conformity with the corresponding storage modes, and supplies the results to the display data DRAM 5 and the character generator 7, respectively.
On receiving the address signal U, the display data RAM 5 reads the character code "G" prestored at the address designated thereby and supplies it to the character generator 7 as the character signal G. The character generator 7 may be a ROM for storing character patterns, for instance. On receiving the character code "G" the character generator 7 selects a pattern (in a matrix configuration) equivalent to one character corresponding to the code and on further receiving the address signal L, outputs the character pattern "P" equivalent to one line in the pattern equivalent to the one character.
In order to generate a fringed pattern, patterns on upper and lower lines are needed, that is, patterns corresponding to three lines are required. Provided that the character pattern "P" to be displayed is indicated when the address signal L is "N" in value, the address signal L within the time required to scan one character width varies in value from "N-1" "N" to "N+1" and character patterns equivalent to three lines within a pattern equivalent to one character are sequentially read onto the pattern signal P (see FIG 2(a)).
Given a period to during which the address selecting circuit 6 supplied with the column selecting signal C horizontally scans a line equivalent in width to one character pattern in order to perform the operation as noted above, the period T0 is itself divided into four periods: T1, T2, T3, T4 (see Fi. 2(b)) and the address selecting circuit 6 operates in the respective periods as follows:
The address selecting circuit 6 applies a read address "Q" generated from the line selecting signal R and the column selecting signal C to the display data RAM 5 as the address signal U during the period T1, hereby the character code "G" stored at the address "Q" in the display data RAH 5 is read onto the character signal G.
The address selecting circuit 6 reads a character pattern on a line adjacent to the line "N" intended for scanning to generate the fringed pattern "Y" during the period T2. Then the address selecting circuit 6 applies "N-1" to the address signal L at this timing during this period. On receiving "N-1" and the character code "G" the character generator 7 reads a pattern on No. "N-1" line from the matrix pattern of the character code "G" as a character signal P.
As the character generator 7 is using the character code "G" during this period, the character code "G" read from the display data RAM 5 onto the character signal G needs to remain stable. Consequently, the address signal U as the input of the display data RAM 5 ought to be stable. Moreover, the address selecting circuit 6 generating the address signal U must apply the address "Q" onto the address signal U.
The character pattern "P" on the line "N" intended for scanning is read to generate the fringed pattern "Y" and to display the original character pattern "P" during the period T3. Then the address selecting circuit 6 applies "N" to the address signal L at this timing during this period. On receiving "N" and the character code "G" the character generator 7 reads a pattern on No. "N" line, that is, the character pattern "P" from the matrix pattern of the character code "G" as the character signal P.
As the character generator 7 is using the character code "G" even during this period, the character code "G" read from the display data RAM 5 onto the character signal G needs to remain stable. Consequently, the address signal U as the input of the display data RAM 5 ought to be stable. Moreover, the address selecting circuit 6 generating the address signal U must apply the address "Q" onto the address signal U.
The address selecting circuit 6 reads a character pattern on a line adjacent to the line "N" intended for scanning to generate the fringed pattern "Y" during the period T4. Then the address selecting circuit 6 applies "N+1" to the address signal L at this timing during this period. On receiving "N+1" and the character code "G" the character generator 7 reads a pattern on No. "N+1" line from the matrix pattern of the character code "G" as a character signal P.
As the character generator 7 is using the character code "G" also during this period, the character code "G" read from the display data RAM 5 onto the character signal G needs to remain stable. Consequently, the address signal U as the input of the display data RAM 5 ought to be stable. Moreover,.the address selecting circuit 6 generating the address signal U must apply the address "Q" onto the address signal U.
In other words, the address selecting circuit 6 generating the address signal U has to keep outputting the address "Q" in a stable condition until the period T0 is terminated after it has read the address "Q" onto the address signal U.
The serial converter circuit 8 has shift registers for converting parallel data to serial data and normally comprises a set of three shift registers as a principal unit in order to process character patterns equivalent to three lines necessary for generating the fringed pattern. This circuit operates to latch the character pattern "P" formed of a plurality of bits and character patterns adjacent thereto on both sides and outputs the character pattern "P" and the fringed pattern "Y" thus generated serially dot-by-dot on receiving the dot clock D.
The image signal generated in the character image signal generating circuit 13 and sequentially output dot-by-dot is superimposed by the apparatus on another image signal E before being displayed on CRT 9.
A description has been given of the character image signal generating circuit 13 of the prior art character display equipment as a specific example. A description will subsequently be given of the write synchronizing circuit 4.
The conventional character display equipment as disclosed in Japanese Laid-Open Pat. No. 124084/1988 and No. 124891/1989, is provided for the purpose of preventing a picture from flickering. More specifically, while the display data RAM 5 is outputting the character code "G" the character code on the character signal G becomes unstable when the address signal A for writing is selected and applied to the address signal U. The character pattern on the pattern signal P output from the character generator 7 as designated by the unstable character code tends to become unstable as well. As a result, because part of the pattern becomes what ought not be displayed, such undesirable flickering appears on the picture. Particularly in the case of the above-mentioned character display equipment capable of displaying fringed characters, the undesirable flickering tends to easily appear on the picture. In order to obviate such an inconvenience, the conventional write synchronizing circuit 4 in the equipment of this kind is designed to output the write synchronizing signal S only during the horizontal and vertical fly-back time of a scanning line (in a so-called ineffective picture period) where no data are read from the display data RAM 5.
However, data transfer speed and timing are restricted in the conventional character display equipment since the ineffective picture period is only utilized to write data to the display data RAM 5. Therefore, the problem is that the microcomputer is kept waiting as the updating of the display picture is slow. This problem is quite common to picture display apparatus such as video movie camera and analog character display equipment having the function of displaying fringed characters.